# Garden of EDA

> A curated, weekly-updated directory of open-source Electronic Design Automation (EDA) tools. Tracks ~150 tools across categories like synthesis, simulation, place-and-route, formal verification, HDL frameworks, and language servers. Pipeline auto-refreshes from GitHub and GitLab every Monday.

## Pages

- [Tools directory (homepage)](https://garden-of-eda.com/): All tools, filterable by category, searchable by name and description.
- [Developers](https://garden-of-eda.com/devs): Top 200 contributors to open-source EDA tools, with their projects and categories.

## Machine-readable data

- [Tools JSON](https://garden-of-eda.com/tools.json): Full catalog as JSON. Each entry includes slug, name, owner, url, description, stars, license, topics, openIssues, pushedAt, category, provider (github/gitlab/static).
- [Devs JSON](https://garden-of-eda.com/devs.json): Top contributors ranked by weighted impact score (commits × log10(repo stars)). Each entry includes login, GitHub profile URL, avatar URL, total contributions, repo count, list of categories they contribute to, and per-repo contribution breakdown.
- [Sitemap](https://garden-of-eda.com/sitemap-index.xml)

## Categories

The catalog uses a fixed taxonomy:

- **agentic-silicon-design**: LLM-driven chip design tools (e.g., coresmith)
- **benchmark**: Evaluation suites for RTL generation (VerilogEval, RTLLM)
- **build-tool**: Hardware build orchestration (FuseSoC, Edalize, Hog, SiliconCompiler)
- **documentation**: Documentation generators and references
- **formal-verification**: Property checking, equivalence checking
- **full-flow**: End-to-end RTL-to-GDS flows (OpenROAD, OpenLane, LibreLane, FABulous)
- **hdl-framework**: Hardware description languages and design frameworks (Chisel, Amaranth, Spade, Veryl, SpinalHDL, pymtl3)
- **hls**: High-level synthesis (XLS, Calyx, PandA-Bambu, Polyphony)
- **ip-core**: Reusable IP libraries (BaseJump STL, PoC)
- **language-server**: LSPs, parsers, and linters for HDLs (slang, svls, rust_hdl, sv-parser, svlint, LazyVerilog)
- **pdk**: Process design kits
- **physical-verification**: Layout vs. schematic, design rule checking
- **place-and-route**: Placement and routing (nextpnr)
- **simulator**: RTL simulators (Verilator, Icarus Verilog, GHDL, NVC)
- **static-timing**: Timing analysis (OpenSTA, OpenTimer)
- **synthesis**: Logic synthesis (Yosys, ABC)
- **testbench**: Verification frameworks (cocotb, VUnit, OSVVM)
- **waveform-viewer**: VCD/FST viewers (GTKWave, Surfer, Vaporview)

## Data refresh cadence

The catalog is regenerated every Monday at 04:00 UTC via a GitHub Actions workflow. Stars, descriptions, and contributor data update weekly. Manual additions and overrides are merged in at the same time.

## Contribute

Missing a tool or have feedback? Open an issue at [github.com/trishinraj/eda-tools-suggestions](https://github.com/trishinraj/eda-tools-suggestions/issues/new).